# A basic S -R flip-flop can be constructed by cross -coupling which basic logic gates : -

21 views
A basic S -R flip-flop can be constructed by cross -coupling which basic logic gates : - a) AND or OR gates b) XOR or XNOR gates c) NOR or NAND gates d) AND or NOR gates

A basic S -R flip-flop can be constructed by cross -coupling which basic logic gates : - NOR or NAND gates

## Related questions

In an unclocked R-S flip flop made of NOR gates, the forbidden input condition is:  (1) R=0, S=0 (2) R=1, S=0 (3) R=0, S=1 (4) R=1, S=1

A single transistor can be used to build which of the following digital logic gates : - a) AND gates b) OR gates c) NOT gates d) NAND gates

By which of the following connections, one-bit binary counter can be obtained from a JK flip-flop?  A) J = K = 0 B) J = K = 1 C) J = K’ D) None of these

To convert a S-R flip-flop to D flip-flop (a) D input is given to S and D input to clock (b) D input is given to S and D to R (c) D input is given to clock and D to S input (d) D input to S and clock to R

Which of the following gates can be used to realize all possible combinational logic functions?  (i) OR gate (ii) NOR gate (iii) Exclusive OR gate (iv) NAND gate (v) AND gate  (A) (iii), (iv) and (v)  (B) (i), (iii) and (iv)  (C) (ii) and (iv)  (D) (i) and (v)

Which of the following describes the operation of a positive edge - triggered D -type flip-flop? a) if both inputs are HIGH, the output will toggle b) the output will follow the input on the leading edge of the clock c) - when both inputs are LOW, an invalid state exists d) the input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.

The output of a JK flip-flop with asynchronous preset and clear inputs is ‘1’. The output can be changed to ‘0’ with one of the following conditions by applying A) J = 0, K = 0 and using a clock B) J = 1, K = 0 and using the clock C) Asynchronous preset input D) J = 1, K = 1 and using the clock

Which of the following flip-flop do not have race problem ? a)T flip-flop b) D flip-flop c) JK flip-flop d) Master Slave flip-flop

Read the following statements: i. Gate is a combinational logic. ii. JK Flip-flop in toggle mode is not combinational logic. iii. MSJK Flip-flop suffers from race-around. iv. Counters are sequential circuits. Which choice is correct? (A) i, ii (B) i, ii, iv (C) ii, iii, iv (D) i, ii, iii

Draw logic diagram of T flip-flop and give its truth table.

In a positive edge triggered JK flip-flop, J = 1, K = 0 and clock pulse is rising, Q will be (a) 0 (b) 1 (c) showing no change (d) toggle

The basic logic gate whose output is the complement of the input is the: - a) OR gate b) AND gate c) inverter d) comparator

A 1ms pulse can be stretched to 1 s pulse by using (A) an astable multivibrator (B) a monostable multivibrator (C) a bistable multivibrator (D) a Schmitt trigger circuit

Whether a given point in the S-plane lies on the Root Locus of a system can be determined by (A) Magnitude criterion (B) Angle Criterion (C) Both Magnitude and Angle Criteria (D) Break-in and Break-away Criteria

A half adder can be constructed from

In a household single phase induction type wattmeter, the meter can be reversed by: - a) reversing the supply terminals b) reversing the load terminal c) opening the meter connection and reversing either the potential coil terminals or current coil terminals d) opening the meter and reversing the connection of both the potential coil terminals and current coil terminals

Among the logic families, the family which can be used at very high frequency greater than 100 MHz in a 4 bit synchronous counter is

In R-L-C series resonant circuit magnitude of resonance frequency can be changed by changing the value of?

Wait status can be achieved in 8085 microprocessor by : - a) TRAP b) DMA c) HOLD d) INTR

The r.m.s. value of a half-wave rectified alternating current is 10 A. Its value for full-wave rectification will be

The 555 timer can be used in which of the following configurations ?  a) astable, monostable b) monostable, bistable c) astable, toggled d) bistable, tristable

Each flip-flop in a 4-bit ripple counter introduces a maximum delay of 40 n sec. The maximum clock frequency is (a) 2.65 MHz (b) 6.25 MHz (c) 5.26 MHz (d) 6.52 MHz

How is a J-K Flip Flop made to toggle  (a) J=0, K=0 (b) J=1, K=0 (c) J=0, K=1 (d) J=1, K=1

In a JK flip-flop, for what input next state is complement of the present state (A)J=0,K=0 (B)J=1,K=0 (C)J=0,K=1 (D)J=1,K=1

A 3 -stage ripple counter has Flip Flop with propagation delay of 25 nsec and pulse width of strobe input 10 nsec. Then the maximum operating frequency at which counter operates reliably is

A J -K flip-flop with J= 1 and K= 1 has a 20 kHz clock input. The Q output is : (A) Constant and low (B) Constant and high (C) A square wave with 20 kHz frequency (D) A square wave with 10 kHz frequency

On a master slave flip-flop, master is enabled : (A) When gate is low (B) When gate is high (C) When gate is either low or high (D) None of the above

A functionally complete operation set of logic gates is  A) AND and NOT B) OR and NOT C) AND and OR D) EXOR and AND

State function of preset and clear in flip flop.

The frequency of the clock signal applied to the rising edge triggered D flip-flop shown in figure is 10 KHZ. The frequency of the signal at Q is A) 10 KHz B) 2.5 KHz C) 20 KHz D) 5 KHz

Define flip-flop.

Transformer coupling is used in class A amplifier to make it : -  a) more efficient b) less bulky c) less costly d) distortion free

What is the size of memory which can be accessed by direct accessing in 8085 microprocessor? A) 64 kB B) 4 kB C) 128 kB D) 128 MB

The property of materials by which they can be drawn into wires is known as: A) malleability B) elasticity C) creep D) ductility

The speed and torque of induction motors can be varied by which of the following means: 1) Stator voltage control 2) Rotor voltage control 3) Frequency control 4) All of these

Thermocouple instruments can be used for a frequency range upto   (a) 100Hz (b) 5000 Hz (c) 1 MHz (d) 50 MHz and above

If a signal band limited to fm is sampled at a rate less than 2fm, then the constructed signal will be A) Large in amplitude B) Small in amplitude C) Distorted D) Distortion less

The complete set of only those Logic Gates designated as Universal Gates is  (A) NOT, OR and AND Gates (B) XNOR, NOR and NAND Gates (C) NOR and NAND Gates (D) XOR, NOR and NAND Gates

A servo motor works on the same basic principle as that of a : - a) two phase induction motor b) single phase induction motor c) three phase induction motor d) synchronous motor

The main advantage of BODE's plot is that multiplication of magnitudes can be converted into : - a) addition b) subtraction c) division d) none of the above

A diode D, resistor R and inductor L and a switch S are connected in series.When a voltage V is applied across the circuit and switch is put on, the voltage across L changes as  A) V(1-exp(-t R/L)) B) Vexp(-t R/L) C) Ldi/dt +Ri D) V(1-t R/L)

The equation of 50 Hz current sine wave having r.m.s. value of 60 A is?