# Successive approximation technique is used for

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Successive approximation technique is used for

Successive approximation technique is used for A to D Conversion

## Related questions

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In successive approximation converter input to the comparator is through (A) DAC (B) Latch (C) Flip-flop (D) Sample and hold circuit

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What is essential for a successive approximation Nbit ADC?  (A) 2N clock pulses for conversion, an up-down counter and a DAC. (B) N clock pulses for conversion, a binary counter and a comparator. (C) 2N clock pulses for conversion and a binary counter only. (D) N clock pulses for conversion, an up-down counter and a DAC.

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In 8 bit successive approximation ADC, clock frequency is 1MHz and reference voltage is 10 V.Conversion time in µS for 5 V input is  A) 4 B) 8 C) 10 D) None of these

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List the different techniques used for signal conditioning in DAS. Explain in brief Any one signal conditioning technique.

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The IC used for 2:1 multiplexer is (A) IC 74150 (B) IC 74151 (C) IC 74153 (D) IC 74157

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Hexadecimal number system is used as a s hand language for representing  1. decimal number 2. binary number 3.octal number 4. all the above

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Companding is a technique used to achieve: -  a) uniform quantization b) delta modulation c) non uniform quantization d) differential quantization

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The technique for remote login is called  (1) web browsing (2) telnet (3) internet telephony (4) all of these

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Typical bit rate in kbps for voice encoding using DM technique is  A) 32-48 B) 48-64 C) 64-128 D) 132-248

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Explain the basic dual slope ADC technique used in digital multimeters with its diagram and measurement cycle.

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Explain energy conservation technique “by improving power quality” for induction motor.

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Explain the pulse width modulation technique for control of AC output voltage.

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Which code is used in constructing k-maps?  A) Hamming code B) 2 out of 5 code C) BCD code D) Gray code

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In standard TTL gates, the totem pole output stage is primarily used to (A) increase the noise margin of the gate (B) decrease the output switching delay (C) facilitate a wired OR logic connection (D) increase the output impedance of the circuit

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A 4 bit counter is used to count from 0,1,2...n. Value of “n” is

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Parity bit check is used to

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Which of the following voltage is used represent binary '1' in digital circuits .   1.0 V 2. 15 V 3. +5 V 4. 25 V

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Which signal of 8085 microprocessor is used to insert wait states ?   (a) Ready (b) ALE (c) HOLD (d) INTR

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The ALE line of an 8085 microprocessor is used to (A) latch the output of an I/O instruction into an external latch. (B) deactivate the chip-select signal from memory devices. (C) find the interrupt enable states of the TRAP interrupt. (D) latch the 8 bits of address lines AD7-AD0 into an external latch.

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Maximum phase distortion is encountered when using the filter approximation  A) Elliptic B) Butterworth C) Chebyshev I D) Inverse Chebyshev

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Output of NAND gate is 0. for three inputs when:

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For the circuit shown in figure, the Boolean expression for the output y in terms of inputs P, Q, R and S is

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Number of control lines required for 16 to 1 multiplexer is

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In a JK flip-flop, for what input next state is complement of the present state (A)J=0,K=0 (B)J=1,K=0 (C)J=0,K=1 (D)J=1,K=1

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What is the Gray code word for the binary number 101011?  (1) 101011 (2) 110101 (3) 011111 (4) 111110

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In quadrilateral speed-time curve of electric traction system, the accelerations during successive time periods are ______ respectively.  (A) positive, negative and negative (B) positive, zero and negative (C) positive, positive and negative (D) positive, negative and zero

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No. of flip-flops used in decade counter (a) 3 (b) 2 (c) 4 (d) None of these

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Which of the following gates can be used to realize all possible combinational logic functions?  (i) OR gate (ii) NOR gate (iii) Exclusive OR gate (iv) NAND gate (v) AND gate  (A) (iii), (iv) and (v)  (B) (i), (iii) and (iv)  (C) (ii) and (iv)  (D) (i) and (v)

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Among the logic families, the family which can be used at very high frequency greater than 100 MHz in a 4 bit synchronous counter is

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E -R modeling technique is a  A) Top -down approach C) Left -right approach B) Bottom -up approach D) None of these

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The technique of using stair case ramp in DVM (Digital Volt Meter) is called  (A) Deflecting torque technique (B) Null balancing technique (C) Controlling torque technique (D) Detaching torque technique

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Which of the following is considered a time domain technique in control systems? (a) Nyquist criterion (b) Bode plot (c) Root locus plot (d) Routh-Hurwitz criterion

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Angles in degrees of pole locations of 4th order Butterworth low pass filter approximation from either real axis are  A) +45,-45,+30,-30 B) +67.5,-67.5,+45,-45 C) +30,-30,+22.5,-22.5 D) +67.5,-67.5,+22.5,-22.5

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If Moor's law continues to hold, predict the approximation number of transistor per leading edge IC in the year. 1.2030 2.2050

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For a NAND gate, when one or more inputs are low then the output will be A) Low B) High C) Alternately high and low D) High or low depending on relative magnitude of inputs

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Determine the output frequency for a frequency division circuit that contains 12 flip–flops with an input clock frequency of 20.48 MHz: (1) 10.24 kHz (2) 5 kHz (3) 30.24 kHz (4) 15 kHz

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Assuming 8 bits for data, 1 bit for parity, I start bit and 2 stop bits, the number of characters that 1200 BPS communication line can transmit is

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Block diagram reduction technique problem 3

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Block diagram reduction technique problem 2

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Block diagram reduction technique problem 1

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Explain energy conservation technique in induction motor by improving mechanical power and transmission efficiency.