Explain estimation of channel capacitance of CMOS.
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Capacitance estimation: The dynamic response i.e. switching speed of MOS system depends on capacitance associated with the MOS devices which are formed by different layers in MOS transistors and interconnection capacitances that are formed by metal, poly and diffusion wires.

The total load capacitance on the output of a CMOS gate is the sum of: 

Gate capacitance of other inputs connected to the output of the gate. 

Diffusion capacitance of the drain connected to the output. 

Routing capacitance i.e. capacitance of interconnects between the output and other inputs.

MOSFET Capacitance: The cross section view and top view of n channel MOSFET is as shown:


The mask length of the gate is indicated by LM and the actual channel length is L. The extent of both the gate-source and the gate-drain overlaps are LD

Hence Channel length L = LM – 2LD. The source and drain overlap region lengths are usually equal to each other because of the symmetry of the MOSFET structure. Generally LD is of order of 0.1µm. Both the source and drain diffusion regions have a width of W. The diffusion region length is denoted by y. These regions surrounded by p+ channel stops implants as it avoids formation of unwanted channels between the two neighboring n+ diffusions. Most of the parasitic device capacitances are due to three dimensional, distributed charge voltage relations within the device structure. 


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