Write the syntax of entity and architecture used in VHDL and explain it.
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Entity declaration: It defines the names. Input output signals and modes of a hardware module. Also it provides the external interface of an entity. It is a black box view.

Syntax: 

entity entity _ name is 

Port declaration. 

end entity_name

Architecture: It describes the internal description of it tells what is thereinside design. Each entity has at least one architecture and an entity can have many architecture. Architecture can be described using structural, dataflow, behavioral or mixed style. Architecture can be used to described a design at different levels of abstraction like gate level (RTL) or behavior level.

Syntax: 

architecture architecture _name of entity_ name 

Architecture_ declaration_ name; 

begin 

Statement; 

end architecture_ name;
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