What do you meant by sensitivity list and zero modeling?
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Sensitivity list: Every concurrent statement has a sensitivity list. Statements are executed only when there is an event or signal in the sensitivity list, otherwise they are suspended. Ex. F<=a and b; A and b are in the sensitivity list of f. the statement will execute only if one of these will change. Ex. Proc ess(clk, RST) The process is sensitive to RST and clk signal i.e. an event on any of these signals will cause the process toresume

Zero Modeling: All digital circuit elements have a delay (propagation delay) which is very small in terms of nano sec. This nano sec delta delay will have little impact while writing the VHDL code. But for circuit realization this delay must be incorporated. The physical circuit always has finite delay.The ordering of zero delay events is handled with a fictitious unit called delta time. Delta time represents the executionof a simulation cycle without advancing Simulation time. The simulator models zero-delay events using delta time.Events scheduled at the same time are simulated in specific order during a delta time step.Related logic is then resimulated to propagate the effects for another delta timestep. Delta time steps continue until there is no activity for the same instant of simulated time
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