Test Bench: A test bench is used to verify the functionality of the design. We need to stimulate our designs in order to test their functionality. Stimulus in a real system is from an external source, not from our design. We need a method to test our designs that is not part of the design itself. This is called a "Test Bench”. Test Benches are VHDL entity/architectures. We initiate the design to be tested using components. We call these instantiations "Unit Under Test" (UUT) or "Device Under Test". The entity has no ports .We create a stimulus generator within the architecture. We can use reporting features to monitor the expected outputs.
Applications: 1. A test bench is used to verify the functionality or correctness of the design. 2. It is useful to generate stimulus for stimulation. 3. It is used to analyze the design to compare the result of two simulations. 4. To compare the results of two simulations. 5. To apply this stimulus to the entity under test and to collect output responses. 6. To compare output responses with expected values.