Specifications: In this step all the functionality and features are defined, such as power consumption, voltage reference, timing restrictions and performing criterion. Chip planning is also performed in this step. The next step is to decide the architecture for the design from the specification. RTL Coding: This is beginning of the ASIC design flow. The micro architecture is transformed into RTL code, RTL is expressed usually in Verilog or VHDL, by using a HDL one can describe any hardware (digital) at any level. Simulation: Functional/Logical Verification is performed at this stage to ensure the RTL designed matches the idea. Synthesis: Once Functional Verification is completed, the RTL is converted into an optimized Gate Level Net list. This step is called Logic/RTL synthesis. This is done by Synthesis Tools such as Design Compiler (Synopsys), Blast Create (Magma), RTL Compiler (Cadence) etc... A synthesis tool takes an RTL hardware description and a standard cell library as input and produces a gate-level net list as output. The resulting gate-level net list is a completely structural description with only standard cells at the leaves of the design. At this stage, it is also verified whether the Gate Level Conversion has been correctly performed by doing simulation. Physical Implementation: The next step in the ASIC flow is the Physical Implementation of the Gate Level Netlist. The Gate level Netlist is converted intogeometric representation. The geometric representation is nothing but the layout of thedesign. The layout is designed according to guidelines based on the limitations of thefabrication process. The Physical Implementation step consists of three sub steps; Floor planning, Placement, Routing. The file produced at the output of the Physical Implementation is the GDSII file. It is the file used by the foundry to fabricate the ASIC. Physical Verification is performed to verify whether the layout is designed according the rules. For any design to work at a specific speed, timing analysis has to be performed. We need to check whether the design is meeting the speed requirement mentioned in the specification. This is done by Static Timing Analysis Tool; it validates the timing performance of a design by checking the design for all possible timing violations for example; set up, hold timing. After Layout, Verification, Timing Analysis, the layout is ready for Fabrication. The layout data is converted into photo lithographic masks. After fabrication, the wafer is diced into individual chips. Each Chip is packaged and tested.