For the racing around to take place, it is necessary to have the enable input high along with J=K=1. As the enable input remains high for a long time in a JK latch, the problem of multiple toggling arises. But in edge triggered JK flip flop, the positive clock pulse is present only for a very short time. Hence by the time the changed outputs return back to the inputs of NAND gates 3 and 4, the clock pulse has died down to zero. Hence the multiple toggling cannot take place. Thus the edge triggering avoids the race around condition.